This application claims priority to Japanese Patent Application Number JP2001-281295 filed Sep. 17, 2001, which is incorporated herein by reference.
1. Field of the Invention
This invention relates to a solid-state imaging device having a structure having a plurality of photoelectric converting elements each configuring an imaging pixel to read out photo-charges stored on the photoelectric converting elements by the use of a plurality of transistors, and to a method for manufacturing same. More particularly, the invention relates to a solid-state imaging device to be made in a reduced size and voltage, and to a method for manufacturing same.
2. Description of the Related Art
Conventionally, as a solid-state imaging device of the above kind, there has been a proposal of a MOS-type solid imaging device having, in each imaging pixel, a photodiode for photoelectric conversion and various MOS transistors for transferring, selecting, amplifying and resetting the photo-charges stored on the photodiode.
FIG. 5 is a circuit diagram showing a configuration example of a related-art pixel part in such a MOS-type solid-state imaging device.
FIG. 5 shows a configuration up to outputting the photoelectrons stored on a photodiode 10 onto a vertical signal line 12, wherein the vertical signal line 12 has, at its lower end, a voltage output to a signal processing circuit of a hereinafter-referred S/H-CDS circuit.
Meanwhile, the vertical signal line 12, at an upper end, is connected to a load transistor 14 serving as a constant-current source at the outside of the pixel part.
As shown in the figure, four MOS transistors 20, 22, 24, 26 are provided around the photodiode (hereinafter, referred to as PD) 10.
At first, a reset transistor 20 and a transfer transistor 22 are connected in tandem between a drive power source (drive voltage Vdd) and the PD 10. A floating diffusion region (hereinafter, referred to as FD region) 16 is provided between a source of the reset transistor 20 and a drain of the transfer transistor 22.
Meanwhile, a select transistor 24 and an amplifier transistor 26 are connected in tandem between the vertical signal line 12 and the drive power source (drive voltage Vdd). The amplifier transistor 26 has a gate connected to the FD region 16.
A reset pulse is inputted to a gate of the reset transistor 20, a transfer pulse is to a gate of the transfer transistor 22, and select pulse is to a gate of the select transistor 24.
In this structure, in case the select transistor 24 is turned ON, the amplifier transistor 26 and the constant-current source 14 at the outside of the imaging region constitute a source follower. Consequently, the potential on the vertical signal line 12 has a value following a gate voltage of the amplifier transistor 26, i.e. a potential at the FD region 16, which is inputted to a signal processing circuit.
Note that actually a plurality of pixel parts are connected to one vertical signal line so that a particular pixel can be selected by the select transistor 24.
In the meanwhile, the conventional solid-state imaging device as in the above has a defect that the pixel is difficult to reduce in its size because PD and four transistors are required in one pixel.
Accordingly, it is one of the major problems to decrease, to what extent, the area the transistors occupy of the pixel area in order to increase the area for the PD.
Meanwhile, in the imaging region entirety, there are arranged in series, on the current path thereof, select transistors, amplifier transistors and diffusion layers between them. In a particularly small pixel, the transistor is small in its W length to increase resistance, resulting in a problem that voltage reduction is difficult due to the amount of voltage drop and noise increases.
It is an object of the present invention to provide a solid-state imaging device that is possible to reduce the arrangement area of the amplifier and select transistors in each of a plurality of pixel parts, thus enabling the reduction in size, voltage, noise and the like, and a method for manufacturing the same.
The present invention is characterized by having an imaging section having a plurality of pixel parts, the pixel part comprising: photoelectric converting means for storing photo-charge depending upon an amount of light reception; an amplifier transistor for taking out a signal corresponding to the photo-charge stored on the photoelectric converting means; a select transistor for connecting selectively an output of the amplifier transistor to a signal line that is connected to a current source at an outside of the imaging section; a gate electrode of the pixel part formed at least in a two-level structure; a gate electrode of the amplifier transistor formed in a first level of the two-level structure; and a gate electrode of the select transistor formed in a second level of the two-level structure.
Also, the invention is characterized by having an imaging section having a plurality of pixel parts, the pixel part comprising; photoelectric converting means for storing photo-charges depending upon an amount of light reception; an amplifier transistor for taking out a signal corresponding to the photo-charge stored on the photoelectric converting means; a select transistor for connecting selectively an output of the amplifier transistor to a signal line that is connected to a current source at an outside of the imaging section; a gate electrode of the pixel part formed at least in a two-level structure; a gate electrode of the amplifier transistor formed in a first level of the two-level structure; and a gate electrode of the select transistor formed in a second level of the two-level structure; wherein the select transistor has a channel layer formed self-aligned by implanting ions to a region below the gate electrode of the select transistor after forming a gate electrode of the amplifier transistor in the first level.
According to the solid-state imaging device of the invention, the gate electrode of the pixel part is formed in a two-level structure wherein the gate electrode of the amplifier transistor is formed in a first level of the two-level structure and the gate electrode of the select transistor is formed in a second level of the two-level structure. Consequently, because the gate of the amplifier transistor and the gate of the select transistor can be closely arranged without a spacing, it is possible to reduce the arrangement space of the amplifier and select transistors. This contributes to size reduction of the solid-state imaging device entirety due to the size reduction in the pixel parts. Correspondingly, the arrangement space of the photoelectric converting means can be enlarged, making possible to contribute to the improvement in imaging sensitivity.
Meanwhile, because the amplifier transistor and the select transistor are closely arranged, the resistance on a current path can be reduced to realize the reduction in voltage and noise.
According to the method for manufacturing a solid-state imaging device of the invention, the gate electrode of the pixel part is formed in a two-level structure wherein the gate electrode of the amplifier transistor is formed in a first level of the two-level structure and the gate electrode of the select transistor is formed in a second level of the two-level structure. This can reduce the arrangement space of the amplifier and select transistors, thus contributing to size reduction of the solid-state imaging device entirety due to the size reduction in the pixel parts. Correspondingly, the arrangement space of the photoelectric converting means can be enlarged, making possible to contribute to the improvement in imaging sensitivity.
Meanwhile, because the amplifier transistor and the select transistor are closely arranged, the resistance on a current path can be reduced to realize the reduction in voltage and noise.
Furthermore, in this manufacturing method, a channel layer of the select transistor is formed self-aligned by implanting ions to a region below the gate electrode of the select transistor after forming a gate electrode of the amplifier transistor in the first level. Consequently, the amplifier transistor can be suppressed from deviating in characteristic. Eliminated is a potential gap as encountered in the two-level gate.